The present invention relates to a processor's interface with peripheral devices and more particularly to circuitry for the elimination of marginal timing between a microprocessor and its associated peripheral devices.
It is desirable for microprocessors to achieve a high data transfer rate between itself and its associated peripheral devices. This high data transfer rate provides the highest microprocessor throughput. High microprocessor throughput is desirable since this allows the microprocessor to perform more functions per unit of time.
Peripheral devices may include memories, disk drives, tape drives, internal or external registers. These peripheral devices have markedly different access times for reading and writing under microprocessor control. Typically, a different peripheral device interface may be required for these different peripheral devices. Several different interface circuits is not economical. This would conserve considerable space and power.
In addition, a processor is required to interface to a number of different peripheral devices. These peripheral devices have different data transfer rates and different timing. A solution to this problem is to design, simulate and test a unique interface circuit for each peripheral. This requires physical space for each of the circuits as well as being wasteful of components, power and design effort.
Accordingly, it is an object of the present invention to provide a generic processor interface controller which eliminates marginal and different timings between a processor and a number of peripheral devices.